When interfacing with an input/output (I/O) device, an I/O interface is used. So that the I/O interface may communicate properly with the I/O device, a certain output voltage swing is typically desired. This voltage swing may be provided by a driver circuit situated within the I/O interface. The driver circuit may be in the form of a microprocessor device.
Microprocessor devices typically are powered by voltage supplies that may provide, for example, a voltage swing between 0 and Vdd1. This voltage swing may be different than the voltage swing requirements of an external device to which the interface is coupled. For example, the I/O device may desirably rely upon a voltage swing between 0 and Vdd2 volts. The difference between Vdd1 and Vdd2, if any, will depend on requirements of desired applications. In most applications, Vdd2 is greater than Vdd1. For example, Vdd2 may be 3.3 volts while Vdd1 may be 2.5 volts.
If the microprocessor voltage swings between 0 and Vdd1 and the external device relies upon a voltage swing between 0 and Vdd2, a conversion is desirably implemented so that the driver circuit and the external device may communicate. To enable this communication, a translation circuit may be used. Various circuits for performing such conversions are well known in the art.
In some applications, it is desirable not only to use the driver circuit to translate between voltage swings, but also as part of a receiver environment. A driver circuit 300 configured for use in such an environment is illustrated in FIG. 3. Translation circuitry is represented in FIG. 3 by: (i) nFET 320 and nFET 322, configured as a first pass gate, and (ii) pFET 324, pFET 326, and nFET 328, configured as a half-latch. The translation circuitry amplifies a data signal 308 applied to input terminal 310. In particular, the voltage swing of data signal 308 is amplified from a swing between 0 and Vdd1 volts to a swing between 0 and Vdd2 volts. The amplified data signal is provided to an output stage of driver circuit 300 which includes "top" pFET 304 and "bottom" pFET 306. Both pFETs 304 and 306 are coupled to the external circuitry through output terminal 302, and function to drive the external circuitry at a level of Vdd2 volts when data signal 308 has a state of logical `1`, i.e., a level of Vdd1 volts.
Driver circuit 300 interfaces with an off-chip receiver (not shown) through a conventional I/O interface at output terminal 302. In some applications, the receiver voltage swings between 0 and Vdd3, where Vdd3 is greater than Vdd1 and Vdd2. In one example, the driver circuit translates a signal which swings between 0 volts and 2.5 volts to a signal which swings between 0 volts and 3.3 volts, and the receiver operates at 5 volts. Because the receiver is coupled to output terminal 302 of driver circuit 300, it is possible that Vdd3 may be passed from the receiver to driver circuit 300. If Vdd3 sufficiently exceeds Vdd1 and Vdd2, voltage Vdd3 could cause improper operation of driver circuit 300 and potentially destroy transistors within driver circuit 300. To prevent these effects, driver circuit 300 includes feedback circuitry, represented by transistors 258, 260, 262, and 264, configured as illustrated in FIG. 3. The feedback circuitry is coupled between output terminal 302 and "top" pFET 304 of the output stage to deactivate pFET 306 at times when Vdd3 is received at output terminal 302.
As illustrated in FIG. 3, driver circuit 300 further includes nFET 314, and pFETs 316 and 318, configured as a second pass gate. This second pass gate is coupled between input terminal 310 of driver circuit 300 and "top" pFET 304 of the output stage. In this way, the pass-gate circuitry isolates transistors in driver circuit 300 from Vdd3 at times when Vdd3 is received from the external circuitry at output terminal 302.
Some of the pFETs in driver circuit 300 share a common n-well 312. To bias n-well 312, driver circuit 300 includes bias circuitry represented in driver circuit 300 by pFETS 250, 252, 254, and 256, configured as illustrated in FIG. 3. This bias circuitry is coupled between output terminal 302 and n-well 312 shared by pFETs 304 and 306. When Vdd3 is received at output terminal 302, the bias circuitry responds by biasing n-well 312 to a potential substantially as high as Vdd3.
As performance requirements imposed on modern driver circuits become increasingly demanding, it becomes more important to control the slew rate, or switching rate, of the output of a driver circuit. Otherwise, noise levels in the driver circuit could be so great as to hinder the overall performance of the circuit itself and the I/O interface in which it is situated. In addition, to satisfy higher performance requirements, it becomes more important to minimize the number of functional blocks of circuitry, or "stages," in the driver circuit. This, in turn, increases the switching speed of the driver circuit in response to the input data signal 308 changing states. Circuits such as driver circuit 300 do not include means, however, for readily controlling slew rate. In addition, stages of driver circuit 300 may be eliminated, particularly the pass gate circuitry, thus increasing circuit speed while achieving the same overall functionality.